The present embodiments relate to signal processing and are more particularly directed to digital signal processing circuits, systems, and methods implementing approximations for logarithm and inverse logarithm.
Digital signal processing is prevalent in numerous types of contemporary technologies, and it involves various types of devices, signals, and evaluations or operations. For example, devices involved in signal processing may include a general purpose digital signal processor (“DSP”), an application specific processor, (“ASP”), an application specific integrated circuit (“ASIC”), a microprocessor, or still others. The types of processed signals may include various types of signals, where audio signals are one relevant example for reasons detailed below. The operations on these signals may include numerous logic and arithmetic-type operations, where such operations may occur with a general purpose arithmetic logic unit or dedicated hardware/software included within the device performing the signal processing. The present embodiments arise within these contexts, as further explored below.
Given the various device types, signals, and operations involved in signal processing, it is recognized in connection with the present embodiments that the precision involved with some types of signal processing may be between the highest levels demanded in some contexts and the lower levels allowed in others. For example, the precision expected of a mathematical calculation performed by a hand held calculator or central processing unit may be considered to define a standard that is relatively high, while the precision required of some other signal processing may be lower than this high standard. One example where lower precision in signal processing may arise is in an audio signal processor or processing system. Such a system may perform various signal processes and then in response output an audio signal to be played by a speaker or the like. Since the human ear is forgiving of various signal fluctuations, then likewise the signal processing involved may have a lesser standard of precision than is required of the above-mentioned examples of a hand held calculator or central processing unit. However, some audio applications may demand or at least benefit from slight or greater than slight improvements in sound signal processing. Consequently, the present embodiments have particular application for this and other instances of signal processing that require a moderate level of signal evaluation precision between the extremes of high and low precision.
By way of further background, note that some contemporary digital processing systems implement relatively costly solutions to signal processing. For example, the present embodiments provide approximations to the functions of logarithms and inverse logarithms. Thus, where the present embodiments are not used, alternative systems may require sophisticated arithmetic logic units or the like to perform these functions. Such approaches may cause numerous problems, such as increasing device size, complexity, and consequently, device cost. Moreover, in some implementations these increases are simply unacceptable, in which case designs in their entirety may have to be discarded or, at a minimum, considerably altered given the overall system specifications.
By way of still further background, the present inventor has previously invented what is described in U.S. Pat. No. 6,289,367 (hereafter, “the '367 Patent”), issued Sep. 11, 2001, entitled, “Digital signal processing circuits, systems, and method implementing approximations for logarithm and inverse logarithm”, and hereby incorporated herein by reference. As its title suggests, the inventive teachings of the '367 Patent are directed to approximations for the logarithm and inverse logarithm functions. In the '367 Patent, the concept of a “most significant digit” is described, which also is detailed below and has application in the present preferred embodiments. The '367 Patent also teaches that a logarithm can be broken into an integer and decimal portion, where the integer is identified in the Patent by locating the MSD and then additional operations are performed with respect to the determining the decimal portion or an approximation thereof. By way of contrast, the preferred embodiments also identify the MSD, but thereafter alternative steps are used to obtain greater precision in the logarithm approximation as opposed to that in the '367 Patent.
In view of the above, there arises a need to address the drawbacks of prior systems which require complex implementations to determine logarithmic functions and, when needed, to improve the precision provided by the '367 Patent. The preferred embodiments are directed to these concerns.